In synchronous integrated circuits, the integrated circuit is clocked by an external clock signal and performs operations at predetermined times relative to the rising and falling edges of the applied clock signal. Examples of synchronous integrated circuits include synchronous memory devices such as synchronous dynamic random access memories (“SDRAMs”), synchronous static random access memories (“SSRAMs”), and packetized memories like SLDRAMs and RDRAMs, and include other types of integrated circuits as well, such as microprocessors. The timing of signals external to a synchronous memory device is determined by the external clock signal, and operations within the memory device are typically synchronized to external operations. For example, commands are placed on a command bus of the memory device in synchronism with the external clock signal, and the memory device must latch these commands at the proper times to successfully capture the commands. To latch the applied commands, an internal clock signal is developed in response to the external clock signal, and is typically applied to latches contained in the memory device to clock the commands into the latches. The internal clock signal and external clock must be synchronized to ensure the internal clock signal clocks the latches at the proper times to successfully capture the commands. In the present description, “external” refers to signals and operations outside of the memory device, and “internal” refers to signals and operations within the memory device. Moreover, although the present description is directed to synchronous memory devices, the principles described herein are equally applicable to other types of synchronous integrated circuits.
Internal circuitry in the memory device that generates the internal clock signal necessarily introduces some time delay, causing the internal clock signal to be phase shifted relative to the external clock signal. As long as the phase-shift is minimal, timing within the memory device can be easily synchronized to the external timing. However, with higher frequency clock signals, the time delay introduced by the internal circuitry becomes more significant. This is true because as the frequency of the external clock signal increases, the period of the signal decreases and thus even small delays introduced by the internal circuitry correspond to significant phase shifts between the internal and external clock signals. As a result of inherent delays, the commands applied to the memory device may no longer be valid by the time the internal clock signal clocks the latches.
To synchronize external and internal clock signals in modern synchronous memory devices, a number of different approaches have been considered and utilized, including delay locked loops (“DLLs”), as will be appreciated by those skilled in the art. As used herein, the term synchronized includes signals that are coincident and signals that have a desired delay relative to one another. FIG. 1 illustrates a conventional DLL circuit 100 for providing an approximate delay that closely matches the phase difference between input and output clock signals. The DLL circuit 100 uses a feedback configuration that operates to feed back a phase difference-related signal to control one or more delay lines, such as a coarse delay line 112 or a fine delay line 116, for advancing or delaying the timing of one clock signal to “lock” to a second clock signal.
An external clock signal is initially applied to the DLL circuit 100 and received by an input buffer 104 that provides a buffered clock signal DLY_REF to the DLL circuit 100. The DLY_REF signal is delayed relative to the external clock signal due to a propagation delay of the input buffer 104. The DLY_REF signal is then applied to coarse and fine delay lines 112, 116, which include a number of delay stages that are selected by a shift register 120 to apply a measured delay for adjusting the phase of the DLY_REF signal. The shift register 120 controls adjustments to the coarse and fine delay lines 112, 116 by providing shift control signals 134 in response to receiving control signals from a phase detector 130. In response to the shift control signals 134, the coarse delay line 112 applies a measured delay to adjust the phase of the DLY_REF signal near the desired phase for achieving the phase lock condition. The fine delay line 116 provides smaller delay adjustments to “fine tune” the DLY_REF signal closer to the desired phase lock condition. The coarse and fine delay lines 112, 116 generate an output signal CLK_OUT, whose phase is compared to the DLY_REF signal to determine whether the locking condition has been achieved. The CLK_OUT signal is provided to a model delay circuit 140 that duplicates inherent delays added to the applied external clock signal as it propagates through the delay loop, such as the input buffer 104 The model delay circuit 140 then provides a feedback signal DLY_FB to the phase detector 130. The phase detector 130 compares the phases of the DLY_REF signal and the DLY_FB signal to generate shift selection signals 132 to the shift register 120 to control the coarse or fine delay lines 112, 116. The shift selection signal instructs the shift register 120 to increase the delay of the coarse or fine delay lines 112, 116 when the DLY_FB signal leads the DLY_REF signal, or decrease the delay in the opposite case.
While the conventional DLL circuit 100 may adequately provide delay adjustments using the fine and coarse delay lines 112, 116, it is not without drawbacks. The DLL circuit 100 may take several cycles of the DLY_REF signal propagating through the coarse and fine delay lines 112, 116, making several attempts to properly adjust the DLY_REF signal before a locking condition is found, thereby further delaying the overall operation of the memory device. At higher clock frequencies, the DLL circuit 100 may not adequately control the coarse delay line 112, resulting in overcompensated adjustments. In such case, the DLL circuit 100 is required to restart the locking sequence, causing further delays and mismatched clock signals. For example, when the input and output clock signals are out of phase, the signal skew increases, resulting in faulty data transfers and undesired delays until the DLL circuit 100 locks again.
Other DLL circuits have been designed where the delay-locked loop is preset by a measurement function during an initialization mode. The phases of the internal and external clocks are placed in close proximity to each other by a predetermined delay adjustment during the initialization mode, thereby speeding up the locking time. However, DLL circuits that include initialization modes rely on additional circuitry, such as extra model delay circuits, switches and other logic components for measuring the predetermined delay. Inclusion of excess circuitry, adds further delays to the overall operation of the DLL circuit, utilizing more chip space and consuming more power. Furthermore, when model delay circuits are included for replicating delays within the delay loop, an exact delay match is rarely achieved due to design limitations of matched components as is known in the art. Mismatched delays generally result in the clock signals being out of phase and affect the DLL circuit's ability to achieve an accurate phase lock condition as described above.
Therefore, there is a need for a DLL circuit that more accurately achieves a faster locking state, and that reduces the use of excess circuitry, thereby reducing the overall size of the circuit and the consumption of power and space.